The chip design methodology for crosstalk (voltage induced on a victim wire caused by one or more adjacent switching wire(s) called the perpetrator(s)) noise analysis is designd for preventing hardware functional failures. Crosstalk creates unwanted noise pulses on quiet nets which when large enough cause the receiver on the quiet net to amplify the noise and propagate the error signal to a latch which can capture and store it. The crosstalk noise analysis is performed during chip wire routing and any design changes needed are made to those nets which exceed the allowed noise voltage limits. It is very important to prevent hardware failures since noise problems are due to complicated switching interactions and thus are very difficult to detect, diagnose and repair. Currently it is usually the chip design practice to use full net extraction programs such as Cadence Design's Dracula which take 24 hours or more for complicated chips, require a net list or schematic, and only give coupling capacitance (not the noise voltage).
However, even with such time consuming analysis experience with a high performance chip shows that undesirable signal coupling or crosstalk between adjacent long wires can create large enough noise voltages to cause system errors. In our previous generation chips, these noise voltages, created during scanning of test patterns, caused some of the latches in the test to store the wrong value.